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🏗️ - Designing / digital / 3v3 cell library
Between 2026-05-31 11:59 p.m. and 2026-07-01 12:00 a.m.
RebelMike
2026-06-09 6:27 p.m.
One thing I've only just spotted on these latches is the output is inverted (at least according to the verilog and the lib, so I assume it really is). That was surprising to me!
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